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VexRiscv

处理器 SpinalHDL

A FPGA friendly 32 bit RISC-V CPU implementation

Soft-core processors and SoC designs that turn an FPGA into a programmable compute unit.

The project covers topics such as cpu, fpga, riscv, soc, softcore, spinalhdl, verilog, vhdl.

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Stars3,305
Forks522
LanguageAssembly
LicenseMIT
Last push2026-10-13
Repositoryhttps://github.com/SpinalHDL/VexRiscv
View source and README on GitHub

Topics

cpufpgariscvsocsoftcorespinalhdlverilogvhdl

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