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vivado-risc-v

处理器 eugene-tarassov

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Soft-core processors and SoC designs that turn an FPGA into a programmable compute unit.

The project covers topics such as arty-a7, boom, fpga, genesys2, kc705, linux, nexys-video, risc-v.

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Stars1,104
Forks256
LanguageTcl
LicenseNOASSERTION
Last push2026-11-09
Repositoryhttps://github.com/eugene-tarassov/vivado-risc-v
View source and README on GitHub

Topics

arty-a7boomfpgagenesys2kc705linuxnexys-videorisc-v

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