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darkriscv

处理器 darklife

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Soft-core processors and SoC designs that turn an FPGA into a programmable compute unit.

The project covers topics such as core, fpga, risc-v, riscv, verilog.

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Stars2,638
Forks332
LanguageVerilog
LicenseBSD-3-Clause
Last push2026-11-08
Repositoryhttps://github.com/darklife/darkriscv
View source and README on GitHub

Topics

corefpgarisc-vriscvverilog

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