Zynq UltraScale+ MPSoC: PCIe High-Speed Transfer Guide

Fig: PCIe high-speed transfer across MPSoC PS and PL

The Zynq UltraScale+ MPSoC integrates a processing system (PS) and programmable logic (PL), and PCIe is a common high-speed channel connecting a host to FPGA acceleration logic.

Key development steps include: instantiating the PCIe hard IP in PL with link training and BAR configuration; configuring RC/EP mode and DMA drivers under Linux in PS; and moving bulk data via interrupt-driven descriptor rings.

For bandwidth, first estimate theoretical throughput from link rate and width, then verify with measurement tools; watch the impact of MSI/MSI-X interrupts and cache coherency. Related boards and video tutorials are available in our dev board and video modules.

A typical data path: the PL-side PCIe hard IP and DMA move data through descriptor rings, while the PS-side Linux program handles configuration and interrupts. Estimate theoretical bandwidth from link rate and width, then measure throughput to locate bottlenecks.