FPGA Knowledge Base
Top questions from fpga.love AI Q&A
Popular Questions
Vivado
Vivado error: Timing not met (negative WNS) - what to do?
Analyze timing violations and optimization: pipelining, constraints, logic simplification, resource allocation.
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Verilog
Blocking vs non-blocking assignments in Verilog: how to choose?
Use non-blocking for sequential logic and blocking for combinational in always blocks to avoid races and sim/synth mismatch.
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Zynq
How do PS and PL communicate on Zynq?
Common methods: AXI (GP/HP/HPM), interrupts, shared memory - choose by bandwidth and latency needs.
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Selection
Which FPGA board should beginners choose?
Recommendations by goal: Artix-7 for pure Verilog, Zynq-7020 for Linux, domestic FPGAs on a budget.
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Petalinux
Petalinux compiles slowly - what to do?
Speed up with parallel builds, incremental builds, sstate cache cleanup, SSD, fewer packages.
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Browse by Category
Verilog Basics
Syntax, timing, FSM, testbench, synthesizable style
32 Articles
Vivado Tools
Synthesis, implementation, constraints, errors, simulation, debug
48 Articles
Zynq Development
PS/PL, AXI, DMA, interrupts, bare-metal, RTOS
26 Articles
Linux Drivers
Device tree, char devices, SPI, I2C, DMA, driver development
18 Articles
Domestic FPGA
Ziguang Tongchuang, Anlogic, Gowin, Fudan Micro, compatibility issues
15 Articles
Selection & Tools
Board selection, model comparison, version differences, toolchains
21 Articles
Latest Entries
Vivado
What’s the difference between Vivado 2025 and 2023?
New Versal AI support, timing analysis improvements, faster compile, legacy project compatibility.
2026-10-28 · 128 reads
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Zynq
How much faster is Zynq-7020 vs 7010?
Logic cells, DSP, BRAM, CPU frequency comparison and selection advice.
2026-10-27 · 96 reads
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Domestic FPGA
Can the Ziguang Tongchuang PGL22G replace Artix-7?
Resource comparison, toolchain compatibility, migration effort, performance, domestic replacement notes.
2026-10-26 · 215 reads
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