ALINX Cloud Classroom52:42ALINX Cloud Classroom Ep.15 | FPGA KEY Button Experiment | Debounce Theory, Project Setup & Debug2026-10-28
ALINX Cloud Classroom00:42ALINX Cloud Classroom | AN5642 Image Capture + ADC Ethernet + OSD Overlay - 3 Live Sessions Preview2026-10-27
New Releases02:12New Release | DZ2 Board | AMD Zynq 7000 SoC XC7Z020 ARM + FPGA Heterogeneous Platform2026-10-22
ALINX Cloud Classroom59:42ALINX Cloud Classroom Ep.14 | Petalinux Installation | App Dev Tools Setup2026-10-20
Events & Expos00:47Events | ALINX Booth | HEA47 Demo - Zynq + Jetson High-Speed Acquisition2026-10-13
ALINX Cloud Classroom47:04ALINX Cloud Classroom Ep.13 | FPGA PLL Experiment | Theory, Project, Simulation & Debug2026-09-30
ALINX Cloud Classroom44:28ALINX Cloud Classroom Ep.12 | ZYNQ MIO Deep Dive | MIO/EMIO GPIO + Button & LED Control2026-09-17
ALINX Cloud Classroom34:16ALINX Cloud Classroom Ep.11 | Embedded Linux Dev Environment: VMware Ubuntu + WSL22026-08-28
ALINX Cloud Classroom1:08:34ALINX Cloud Classroom Ep.10 | FPGA LED Blinky: Design, Simulation & ILA Debug2026-08-26
ALINX Cloud Classroom15:43ALINX Cloud Classroom Ep.9 | ZYNQ RTC Interrupt | Controller Theory + Code Analysis2026-08-25
ALINX Cloud Classroom28:05ALINX Cloud Classroom Ep.8 | Linux First Lesson | Directory Structure + Hardware Interfaces2026-06-16
ALINX Cloud Classroom29:33ALINX Cloud Classroom Ep.7 | FPGA Hardware Foundations: AMD Chip Structure & Schematics2026-06-11
ALINX Cloud Classroom42:08ALINX Cloud Classroom Ep.6 | FPGA Essentials | AMD Chip Structure + Schematics2026-05-30
ALINX Cloud Classroom32:46ALINX Cloud Classroom Ep.5 | FPGA Must-Watch | AMD Chip Structure & Schematics2026-05-29
ALINX Cloud Classroom44:28ALINX Cloud Classroom Ep.4 | ZYNQ Project Setup | 7000 & MPSoC Block Design2026-05-22
Events & Expos00:50Events | ALINX & Ziguang Tongchuang 2024 FPGA Symposium National Tour Complete2024-09-23
Events & Expos01:55Events | Smart Video Data Analysis System at 2024 Automotive Testing Expo China2024-09-04
Events & Expos01:40Events | ALINX at AMD Adaptive Computing Summit - FPGA Hardware Solutions2024-08-02
Vitis AI Dev09:51Vitis AI Dev [04] | XILINX FPGA Tutorial - Run Object Detection Inference Demo2022-12-19
Vitis AI Dev27:17Vitis AI Dev [05] | XILINX FPGA Tutorial - Neural Network Training with Keras2022-12-19
Vitis HLS Dev10:12Vitis HLS Dev [09] | XILINX FPGA Tutorial - Image Corner Detection with Vitis HLS2022-11-14
Vitis HLS Dev09:45Vitis HLS Dev [07] | XILINX FPGA Tutorial - YUV/RGB Conversion with Vitis HLS2022-11-14
Vitis HLS Dev38:43Vitis HLS Dev [02] | XILINX FPGA Tutorial - Optimization Methods (Part 1)2022-11-14
Vitis HLS Dev22:21Vitis HLS Dev [03] | XILINX FPGA Tutorial - Optimization Methods (Part 2)2022-11-14
Vitis HLS Dev08:55Vitis HLS Dev [10] | XILINX FPGA Tutorial - Image Sobel Transform with Vitis HLS2022-11-14
Vitis HLS Dev11:13Vitis HLS Dev [05] | XILINX FPGA Tutorial - Using Xilinx Image Library in Vitis HLS2022-11-14
Vitis HLS Dev06:10Vitis HLS Dev [06] | XILINX FPGA Tutorial - Image Grayscale with Vitis HLS2022-11-14
Vitis HLS Dev07:13Vitis HLS Dev [11] | XILINX FPGA Tutorial - Image Canny Transform with Vitis HLS2022-11-14
Vitis HLS Dev04:55Vitis HLS Dev [13] | XILINX FPGA Tutorial - Image Simulation with Vitis HLS2022-11-14
Vitis HLS Dev08:09Vitis HLS Dev [08] | XILINX FPGA Tutorial - Image Contrast Adjustment with Vitis HLS2022-11-14
Linux Driver Dev51:25Linux Driver Dev [23] | XILINX FPGA Tutorial - AXI DMA IP Loopback Driver2022-09-21
Linux Driver Dev30:07Linux Driver Dev [26] | XILINX FPGA Tutorial - AD9238 & AD7606 Drivers2022-09-21
Linux Driver Dev27:42Linux Driver Dev [25] | XILINX FPGA Tutorial - Multi-Touch LCD Display Driver2022-09-21
Linux Driver Dev31:08Linux Driver Dev [05] | XILINX FPGA Tutorial - Concurrent Processing Driver2022-09-21
Linux Driver Dev26:35Linux Driver Dev [20] | XILINX FPGA Tutorial - UART Driver Framework & Xilinx UART Test2022-09-21
Linux Driver Dev31:31Linux Driver Dev [13] | XILINX FPGA Tutorial - Platform Device + Device Tree Driver2022-09-21
Linux Driver Dev27:21Linux Driver Dev [04] | XILINX FPGA Tutorial - PINCTRL & GPIO Subsystem Drivers2022-09-21
Linux Driver Dev26:35Linux Driver Dev [06] | XILINX FPGA Tutorial - GPIO Input & EMIO Driver2022-09-21
Linux Driver Dev18:49Linux Driver Dev [02] | XILINX FPGA Tutorial - New Char Device Driver Framework2022-09-21
Linux Basics08:50Linux Basics [16] | XILINX FPGA Tutorial - QT + DRM + Gstreamer Camera App2022-08-16
Linux Basics05:50Linux Basics [18] | XILINX FPGA Tutorial - Register Ops from Linux Userspace2022-08-16
Linux Basics36:09Linux Basics [02] | XILINX FPGA Tutorial - Petalinux Apps, Drivers & Boot Scripts2022-08-16
Linux Basics14:06Linux Basics [06] | XILINX FPGA Tutorial - QT & OpenCV Cross-Compile Environment2022-08-16
MPSoC SDK Bare-Metal28:12MPSoC SDK Bare-Metal [63] | XILINX FPGA Tutorial - AD9280 Ethernet Transfer & Waveform Display2022-07-19
MPSoC SDK Bare-Metal14:05MPSoC SDK Bare-Metal [65] | AD7606 Ethernet Transfer & Waveform Display2022-07-19
MPSoC SDK Bare-Metal20:20MPSoC SDK Bare-Metal [59] | AXI DMA AN831 Audio Capture - Vitis Project & Code2022-07-19
MPSoC SDK Bare-Metal18:01MPSoC SDK Bare-Metal [64] | AD9238 Ethernet Transfer & Waveform Display2022-07-19
MPSoC SDK Bare-Metal17:53MPSoC SDK Bare-Metal [61] | 7" Touch Panel Display & Touch - Vitis Project & Code2022-07-19
MPSoC SDK Bare-Metal26:27MPSoC SDK Bare-Metal [60] | 7" Touch Panel Display & Touch - Vivado Project2022-07-19
MPSoC SDK Bare-Metal18:35MPSoC SDK Bare-Metal [58] | AXI DMA AN831 Audio Capture - Vivado Project2022-07-19
MPSoC SDK Bare-Metal30:07MPSoC SDK Bare-Metal [56] | AN5642 Ethernet Transfer & Image Display2022-07-19
MPSoC SDK Bare-Metal17:11MPSoC SDK Bare-Metal [54] | AN5642 Dual Camera Display - Vitis Project & Code2022-07-19
MPSoC SDK Bare-Metal15:10MPSoC SDK Bare-Metal [55] | AN5642 Single Camera Capture & SD Card Storage2022-07-19
MPSoC SDK Bare-Metal14:18MPSoC SDK Bare-Metal [51] | AXI DMA AN9767 Signal Generator - Vitis Project2022-07-19
MPSoC SDK Bare-Metal33:12MPSoC SDK Bare-Metal [53] | AN5642 Dual Camera Display - Vivado Project2022-07-19
MPSoC SDK Bare-Metal22:17MPSoC SDK Bare-Metal [50] | AXI DMA AN9767 Signal Generator - Vivado Project2022-07-19
MPSoC SDK Bare-Metal20:08MPSoC SDK Bare-Metal [48] | AXI DMA SG Principles & Vivado Project2022-07-19
MPSoC SDK Bare-Metal33:30MPSoC SDK Bare-Metal [45] | AXI DMA AD9280 Capture Display - Vitis Project2022-07-19
MPSoC SDK Bare-Metal30:04MPSoC SDK Bare-Metal [44] | AXI DMA AD9280 Capture Display - Vivado Project2022-07-19
MPSoC SDK Bare-Metal17:56MPSoC SDK Bare-Metal [43] | AXI DMA AD9708 Signal Generator - Vitis Project2022-07-19
MPSoC SDK Bare-Metal23:18MPSoC SDK Bare-Metal [42] | AXI DMA AD9708 Signal Generator - Vivado Project2022-07-19
MPSoC SDK Bare-Metal14:07MPSoC SDK Bare-Metal [40] | AXI DMA Data Loopback - Vivado Project2022-07-19
MPSoC SDK Bare-Metal39:45MPSoC SDK Bare-Metal [33] | Dual-Core Bare-Metal Interrupt & Data Exchange2022-07-19
MPSoC SDK Bare-Metal22:49MPSoC SDK Bare-Metal [38] | PS-PL BRAM R/W - Vitis Project & Co-Debug2022-07-19
MPSoC SDK Bare-Metal20:43MPSoC SDK Bare-Metal [36] | PL R/W PS DDR - Vitis Project & Co-Debug2022-07-19
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![MPSoC SDK Bare-Metal [48] | AXI DMA SG Principles & Vivado Project](https://i2.hdslb.com/bfs/archive/8e5b8b2f6a1fe3f009ea748abbee0c0a64667477.jpg)
![MPSoC SDK Bare-Metal [47] | AXI DMA AD7606 Capture & Display](https://i1.hdslb.com/bfs/archive/c27b4b92120e8c82679e4de814bcb00821edf096.jpg)
![MPSoC SDK Bare-Metal [46] | AXI DMA AD9238 Capture & Display](https://i2.hdslb.com/bfs/archive/57d6cb67ab1bbfded4071138916ded6ff6303b04.jpg)
![MPSoC SDK Bare-Metal [45] | AXI DMA AD9280 Capture Display - Vitis Project](https://i1.hdslb.com/bfs/archive/17392d9411972148f6a20b9316936cd9e310c0cd.jpg)
![MPSoC SDK Bare-Metal [44] | AXI DMA AD9280 Capture Display - Vivado Project](https://i1.hdslb.com/bfs/archive/6d61ef662961f45d144dd2d0b58344ac43d29930.jpg)
![MPSoC SDK Bare-Metal [41] | AXI DMA Data Loopback - Vitis Project](https://i1.hdslb.com/bfs/archive/be154f53ea5a74ebdfcf0c85d6d768b232e095f4.jpg)
![MPSoC SDK Bare-Metal [43] | AXI DMA AD9708 Signal Generator - Vitis Project](https://i0.hdslb.com/bfs/archive/1f71698392291d5210fa0cfdf8ed31906ad89d80.jpg)
![MPSoC SDK Bare-Metal [42] | AXI DMA AD9708 Signal Generator - Vivado Project](https://i2.hdslb.com/bfs/archive/f799260e50f847358a6b47327dc9a75f1b2502c1.jpg)
![MPSoC SDK Bare-Metal [40] | AXI DMA Data Loopback - Vivado Project](https://i1.hdslb.com/bfs/archive/153645b1fe52e7156dcf7d8663d153a972e1607e.jpg)
![MPSoC SDK Bare-Metal [39] | AXI DMA Principles](https://i2.hdslb.com/bfs/archive/1b808a1fdebd82765eb636939dbe9758b22b0de0.jpg)
![MPSoC SDK Bare-Metal [33] | Dual-Core Bare-Metal Interrupt & Data Exchange](https://i2.hdslb.com/bfs/archive/a9402de72170eb6df616ca1c9274ac5b03e03138.jpg)
![MPSoC SDK Bare-Metal [38] | PS-PL BRAM R/W - Vitis Project & Co-Debug](https://i0.hdslb.com/bfs/archive/57a43f6089f8c713c84134a6790983944e0bb10f.jpg)
![MPSoC SDK Bare-Metal [37] | PS-PL BRAM R/W - Vivado Project](https://i0.hdslb.com/bfs/archive/1e331b5fed89827f9a83a167dd64776d1899f658.jpg)
![MPSoC SDK Bare-Metal [36] | PL R/W PS DDR - Vitis Project & Co-Debug](https://i2.hdslb.com/bfs/archive/00d64b299e737226c7c4aeb489aed7f8645ac88f.jpg)
![MPSoC SDK Bare-Metal [34] | AXI Bus Protocol](https://i0.hdslb.com/bfs/archive/0c46af2b349ff4854d9ca6fa880ff79f1fa5cc25.jpg)
![MPSoC SDK Bare-Metal [32] | Custom IP - Vitis Project & Code](https://i1.hdslb.com/bfs/archive/0e8348159cf96360462f4add47074f6757eb9bae.jpg)
![MPSoC SDK Bare-Metal [28] | RS485 R/W - Vivado Project](https://i1.hdslb.com/bfs/archive/bc1af2a53dadabdfd99b4bc6c4e05458500eaddf.jpg)
![MPSoC SDK Bare-Metal [19] | SD Card TXT File R/W](https://i1.hdslb.com/bfs/archive/a587aeb2cf7be8870c921cd13518f9bfab8a8bdc.jpg)
![MPSoC SDK Bare-Metal [22] | PS Ethernet TCP Echo Server](https://i2.hdslb.com/bfs/archive/e4c7be9fb9f59a3d3f1125c4cab4f4fe5746a207.jpg)
![MPSoC SDK Bare-Metal [29] | RS485 R/W - Vitis Project & Code](https://i0.hdslb.com/bfs/archive/2707b8d7540f1e6aa098770d58983db2ae63a0d0.jpg)
![MPSoC SDK Bare-Metal [27] | AXI GPIO Button & LED - Vitis Project](https://i0.hdslb.com/bfs/archive/57ef7961a7ebed9da2bb1fadd2aac258a13a753a.jpg)
![MPSoC SDK Bare-Metal [23] | PL Ethernet TCP Echo Server](https://i1.hdslb.com/bfs/archive/981f28f0330a8be82ad057cfd8dcba2083d2236c.jpg)
![MPSoC SDK Bare-Metal [02] | MPSoC Vivado Project Flow](https://i0.hdslb.com/bfs/archive/cb4202b9effa463d88b9c044db3651a6df7e21a6.jpg)
![MPSoC SDK Bare-Metal [04] | MPSoC Program Flashing (Boot)](https://i2.hdslb.com/bfs/archive/2561aab97dc04d291aef68ed203472cd41fb6a0c.jpg)
![MPSoC SDK Bare-Metal [01] | MPSoC Architecture](https://i0.hdslb.com/bfs/archive/58e4ea06eb88321f1ceaad9501be5882cbd161b9.jpg)
![MPSoC SDK Bare-Metal [03] | MPSoC Vitis Project Flow](https://i1.hdslb.com/bfs/archive/f34a7be30d1caf4d066c9400e246976e1520bb44.jpg)
![MPSoC SDK Bare-Metal [06] | RTC & Interrupt Controller](https://i2.hdslb.com/bfs/archive/706084263f5acd6108df4204c5c192ebfb257a45.jpg)
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![MPSoC SDK Bare-Metal [05] | Batch-Built Vitis Project](https://i1.hdslb.com/bfs/archive/5747f9428113b97ed67ee4717af08c454b243121.jpg)
![MPSoC SDK Bare-Metal [08] | MIO GPIO Structure](https://i1.hdslb.com/bfs/archive/d254f02d371e40c7dc1b062bbb54581460118dc9.jpg)
