Verilator 5.0: Faster Verilog Simulation with Latest SystemVerilog

Fig: Verilog design compiled into a fast C++ model

Verilator, the open-source Verilog simulator, has released version 5.0 with faster compiled simulation and broader support for the latest SystemVerilog features.

Verilator compiles designs into C++ models for execution, suiting large designs and regression testing, and is a key part of open-source FPGA development flows.

Before upgrading, check SystemVerilog syntax usage and third-party library compatibility in your project. Related examples are available in our open-source project module.

Verilator compiles Verilog/SystemVerilog into C++ models before execution, far faster than interpreters. It excels at regression testing of large designs, though some dynamic simulation needs other tools.