How do PS and PL communicate on Zynq?
Zynq
Fig: CPU block and FPGA array connected by bidirectional bus channels — Zynq heterogeneous communication
Common methods: AXI (GP/HP/HPM), interrupts, shared memory - choose by bandwidth and latency needs.
Three Common Channels
AXI buses are the workhorse between PS and PL: the GP port is low-bandwidth, low-latency, ideal for register-style control; the HP port with DMA moves large data streams for acquisition and video; interrupts let the PL notify the PS of events. Picking the channel by bandwidth and latency need is the first step of Zynq heterogeneous design.
Fig: Three common communication channels between PS and PL
Real projects usually combine them: GP for configuration, HP+DMA for data return, and interrupts for asynchronous event sync.