Verilog Utility Modules
Verilog
Fig: Module grid grouped by datapath, control and communication
Synthesizable module library: FIFO, RAM, FSM, UART, SPI, I2C, PWM, with testbenches.
Module Catalog & Verification
Modules are grouped by interface: datapath blocks (FIFO, dual-port RAM) handle buffering and storage, control blocks (FSMs) manage sequencing, and communication blocks (UART, SPI, I2C, PWM) implement peripheral protocols. Each ships with its own testbench — once simulation passes, it can be instantiated directly.
Fig: Three module families are each verified by a standalone testbench before reuse