Platypus Embedded FPGA IP Cores – 100% Open-Source Bitstream and Dev Tools

Platypus Embedded FPGAs

Platypus TM is a family of standardized embedded FPGA (eFPGA) IP cores.

Value Proposition

Platypus is the ONLY commercial eFPGA product backed up by:

Open Architecture Files

The following table shows Platypus eFPGA IP cores currently available (RC) or in development (RM). Platypus eFPGA cores are available as licensable hard IP. (GA=general availability, RC=release candidate, RM=roadmap)

All Platypus eFPGA hardened IP cores are backed up by an open architecture guarantee. Complete machine readable descriptions of standard architectures can be found in the Logiklib open source repository.

Parametrized soft RTL logic wrap the hardened IP core to handle reset, boot-up, security, and bitstream loading. Bitstream programming is done via standardized memory mapped register interfaces (APB, AXI-Lite, or UMI) selectable by the user during design integration.

The Z1000 standard eFPGA architecture has been ported to the GlobalFoundries GF12LP process. The picture below shows the full layout (GDS) of an integration ready Z1000 eFPGA core.

The Z1015 standard eFPGA architecture has been ported to the GlobalFoundries GF12LPP process. Released to general availability in June 2026, the Z1015 is the largest Platypus eFPGA core to date and is the hardened IP at the heart of Zero ASIC’s heterogeneous FPGA chiplet. See the launch announcement for details.

Development Tools

Platypus device programming is done via Logik , an open source fully automated RTL-to-bits SiliconCompiler based toolchain that seamlessly integrates a complete set of industrial strength open source FPGA development tools. The Logik FPGA tool chain includes support for:

To evaluate the Platypus eFPGA cores Logik development tools, download the open source Logik repository and run the ethernet MAC example as shown below. The example demonstrates 100% automated compilation of RTL code into a bitstream for the Z1000 eFPGA. To fully appreciate the elegance of the Logik development tools, we recommend reviewing the simple 60 line Python run script “eth_mac_1g.py”.

git clone https://github.com/siliconcompiler/logik cd logik pip install -e .[test] cd examples/eth_mac_1g python eth_mac_1g.py IP Deliverables Front-end views Deliverables for evaluation, system design, simulation and chip floor-planning.

Deliverables for sign-off level verification and chip tapeout.

Platypus eFPGA cores are available via commercial IP agreements. Contact our team to find out more about licensing terms and availability.