Integrating Speedcore eFPGA IP
While the Speedcore design and integration methodology is highly flexible and can accommodate significant variations in SoC/ASIC development flows, there are some general principles and guidelines which, if followed, will make the development and integration effort simpler, smoother and more efficient:
With the above in mind, a quick summary of the design and integration methodology is as follows:
To learn more about how to integrate Speedcore eFPGA IP in your design, download the " eFPGA Acceleration in SoCs — Understanding the Speedcore IP Design Process (WP008) " white paper.