Yosys + nextpnr: Full Open-Source Synthesis and Place & Route in Practice
Fig. Yosys + nextpnr: Full Open-Source Synthesis and Place & Route in Practice · themed illustration
Yosys (synthesis) + nextpnr (place & route) form the core of the FPGA open-source toolchain; this article walks a real board flow end to end and explains the full chain and its boundaries.
1. The Open-Source Toolchain Family
The core combination: Yosys handles RTL synthesis (Verilog → netlist); nextpnr handles place & route (netlist → bitstream description); on the simulation side use iverilog/Verilator. Together they form a complete open-source chain from RTL to board.
2. Current Device Support
ICE40, ECP5, and Gowin GW1N series have full support; Artix-7 is maturing via projects like fpga-toolchain. When selecting a device, first confirm the open-source toolchain support level to avoid “synthesized but can’t place and route.”
3. Five-Step Hands-On Flow
- Write RTL and constraints (SDC/pin constraints);
- Yosys synthesis: generate the netlist, check hierarchy and resource estimates;
- nextpnr place & route: observe timing reports and congestion;
- Generate the bitstream and verify on board;
- Debug with ILA/logic analyzer or serial prints.
4. Value and Boundaries
The open-source chain suits teaching, prototyping, and small-to-mid designs: zero license cost, scriptable, CI-friendly. Limitations: high-end device support, complex timing constraints, and the IP ecosystem still rely on commercial tools. As a developer, it’s worth mastering the open-source flow as a “second toolchain.”