From Simulation to Board: Three Tools for FPGA Debugging

1. Tool One: Simulation First

testbench is the most cost-effective debugging method. Choose any of iverilog/Verilator/Vivado Simulator; write “stimulus + assertions” tests — don’t just look at waveforms, use assertions to auto-check protocol timing. Coverage thinking: code coverage (every line/branch exercised) + functional coverage (key scenarios tested).

2. Tool Two: On-Chip Logic Analyzer

Simulation’s blind spot is cross-clock and real interfaces (DDR, Ethernet PHY timing). Use on-chip logic analyzers (Vivado ILA / ChipScope / SignalTap) to capture real signals. Key point: reserve debug probe signals in the design in advance, avoiding “board in hand but no probe to tap.”

3. Tool Three: Board-Level Verification Combo

• Print state machines and key variables over UART/network;
• LEDs as the simplest status indicators (color-coded boot, handshake, error);
• Hardware loopback tests: connect TX to RX first to verify the path before bringing in real peripherals.

4. Five-Step Debug Flow

Reproduce → isolate → locate → fix → regress. Worst practice is “patch and pray”: change one thing at a time and regress all cases after each change. High-frequency causes of “simulation passes but board fails” concentrate in asynchronous handling, reset timing, and unconstrained clocks — check these three first.