Wiki›Vivado error: Timing not met (negative WNS) - what to do? · FPGA Knowledge Base

Vivado error: Timing not met (negative WNS) - what to do?

Vivado

FPGA timing violation (negative WNS) cover illustration

Fig: Critical path timing violation — setup margin insufficient, WNS is negative

Analyze timing violations and optimization: pipelining, constraints, logic simplification, resource allocation.

Timing Violation Fundamentals

A negative WNS (Worst Negative Slack) means data does not arrive stably within the setup window before the capturing clock edge. Common causes: too many combinational logic stages, routing congestion, clock skew, and unreasonable constraints.

FF1 Launch FF Comb. Logic Long path / congestion FF2 Capture FF Tdata too long Clock period Tclk: data must settle before setup time Tsu, otherwise WNS < 0

Fig: Data arrives too late on the critical path, leaving negative setup slack (WNS < 0)

To fix it, compress the critical path first: insert pipeline registers to split long paths, refine physical constraints and routing strategy, use set_multicycle_path for multi-cycle paths and set_false_path for false paths, and simplify logic or rebalance resources to reduce single-stage delay.

Related Videos

More FPGA hands-on tutorials on the fpga.love video portal

Video coming soon

Subscribe to fpga.love

Daily Briefing · Weekly Digest · Monthly Deep Dive