Blocking vs non-blocking assignments in Verilog: how to choose?
Verilog
Fig: Register-level circuit with digital waveforms — synchronous logic and assignment
Use non-blocking for sequential logic and blocking for combinational in always blocks to avoid races and sim/synth mismatch.
The two rules are really about modeling semantics: blocking assignments in combinational always blocks take effect immediately in order, modeling real wires; non-blocking assignments in sequential always blocks update all outputs together at the clock edge, modeling flip-flop sampling. Mixing them causes simulation/synthesis mismatch and even races.
Fig: Behavioral difference between blocking and non-blocking assignments
Keep one simple rule: use <= in sequential always blocks and = in combinational ones, and never mix the two within a single always block.