Verilator
EDA
Fig: Netlist transformed into an executable model producing waveforms
Open-source Verilog simulator: fast, with latest SystemVerilog support.
Verilator Simulation Flow
Unlike waveform simulators, Verilator first compiles the Verilog design into an optimized C++/SystemC model, then runs it from a self-provided testbench. It reaches near-hardware speed — ideal for large regression suites — and still dumps standard waveform files for analysis.
Fig: RTL is compiled by Verilator into a C++ model, run under a testbench that dumps waveforms