X-Epic Agentic EDA Digital Flow Solution Seminar Successfully Held

Recently, the X-Epic Agentic EDA Digital Flow Solution Seminar was successfully held in Shenzhen. Representatives from six industry partners and technical experts in the fields of CPU, AI chips, FPGA, storage, and communication chips shared the practical processes and application results of their collaboration with X-Epic, focusing on verification challenges encountered in real projects.

Verification cycles compressed from weeks or months to hours; approximately 18,000 simulation error messages automatically converged to two primary root causes; compilation and simulation performance improved by up to approximately 3x in certain scenarios; manual intervention in regression tasks reduced by 80% to 90%...

These measured results from frontline chip projects are moving the value of Agentic EDA from concept to engineering practice.

From Probabilistic Generation to Trustworthy Results: Building a Full-Flow Technology Matrix

At the seminar, the X-Epic technical team shared three underlying mechanisms that support the trustworthy deployment of Agentic EDA:

Structuring ambiguous intents in design specifications and establishing associations with design code, verification code, technical documentation, and execution results, enabling agents to understand engineering context so that generated content is grounded and traceable.

Key conclusions do not rely on the large model's self-judgment but are instead executed by EDA engines such as simulation, formal verification, and equivalence checking, continuously validating and correcting model outputs through constraint solving, tool feedback, and cross-validation.

Human approval, permission boundaries, and version management are set within task flows, with complete preservation of logs, waveforms, source code, and tool execution results, making every judgment checkable, reviewable, and auditable.

On this trustworthy foundation, a product matrix covering the full chip design and verification flow was further demonstrated:

In the formal verification phase, Formal Agent can complete assertion generation, verification execution, and coverage convergence, and continuously refine based on tool feedback; HEC Agent targets equivalence checking among algorithm models, operators, and RTL, providing a basis for key conclusions through constraint solving and mathematical proof, helping engineers more thoroughly answer "whether verification is sufficient."

When verification enters the simulation and debug phase, Simulation Agent connects test generation, compilation simulation, and result analysis, while Debug Agent further synthesizes logs, waveforms, and source code to locate root causes and output evidence for engineer review. AI thus no longer merely provides a possible answer but can participate in task execution, problem localization, and result accumulation.

As complex SoC scale expands, verification efficiency is also directly constrained by simulation performance. GalaxSim Turbo 3.0 improves system-level simulation efficiency through parallel simulation, model replacement, equivalent rewriting, and formal verification techniques, enabling more software and system scenarios to run fully within limited verification cycles.

As verification advances to the system level, software execution, real device integration, and multi-chip interconnection become new challenges. The X-Epic P2E hardware emulation acceleration platform provides virtual CPU, PCIE Host, and Scale UP Speed Adapter solutions to address debug efficiency, runtime speed, and Chip-to-Chip system-level interconnection verification challenges in complex hardware-software co-verification.

The on-site demo featured a virtual PCIE Host as the PCIE Gen5 master, an XuanTie R908 QEMU model as the virtual CPU subsystem, and Scale UP IP as the Chip-to-Chip interconnection interface, visually and intuitively demonstrating the solution principles and operation of the X-Epic P2E hardware acceleration platform.

When verification scale expands from individual tasks to teams and clusters, resource scheduling and flow management also affect project efficiency.

FusionFlex provides resource reservation, scheduling, monitoring, and statistics for Emulation clusters, and also offers complete regression task management capabilities, handling large-scale regression execution, automatic exception handling, and result aggregation and analysis. It ensures that expensive hardware resources are well-managed and well-utilized while making the entire simulation regression flow more automated, transparent, and efficient.

Validating Agentic EDA with Real Projects

01 GigaDevice: How AI Drives Formal Verification at Scale Amid Long Cycles and High Barriers

Assertion writing, execution, and result analysis for complex modules are highly dependent on expert experience, with verification cycles often lasting weeks or even months. GigaDevice introduced the X-Epic Formal Agent, conducting phased project onboarding across 12 modules and gradually transitioning to autonomous use by customer engineers.

In a module with approximately 74,000 lines of code and over 480 assertions, the solution not only reproduced historical issues but also uncovered new RTL and specification problems; verification efficiency for some modules improved by up to approximately 18x, compressing verification cycles from weeks or months to hours.

02 Anlogic: How to quickly converge on true root causes amid massive repetitive error reports

Large volumes of simulation errors are often triggered repeatedly by a small number of root causes, requiring engineers to continuously screen and cross-reference across logs, waveforms, and source code.

For a DMA module with approximately 25,000 lines of code, 9 random test cases generated approximately 18,000 error reports. X-Epic's Debug agent automatically converged these into two primary root causes, completing single test case analysis in an average of 39 minutes and correlating log, waveform, and source code evidence, helping engineers shift from "reviewing one by one" to "locating by root cause."

03 ZTE Microelectronics: How to reduce platform adaptation costs amid large-scale tool migration

The challenge of simulation toolchain migration is not just whether individual test cases can run, but whether different platforms, configurations, and large-scale regression tasks can be stably supported.

ZTE Microelectronics completed compilation and simulation verification across 80 platforms of varying scales, with 78% of platforms achieving out-of-the-box readiness; platforms that completed regression covered thousands of test cases, with tool performance improving by up to approximately 3x in some scenarios, providing engineering validation for domestic simulation toolchains entering large-scale R&D workflows.

04 Centec Networks: How to conduct system-level verification in advance for complex multi-chip interconnection

High-speed interconnection, real device access, and heterogeneous computing collaboration have expanded verification targets from single chips to complete systems, making it difficult to cover real operating scenarios with software simulation alone.

Centec Networks and X-Epic conducted rate-limited interconnection interop testing for 400G and 800G scenarios during the prototyping verification phase, combining hardware acceleration platforms with real switching equipment to accumulate system-level verification experience for high-speed interconnection adaptation and heterogeneous computing resource pooling.

05 Sunrise: Large-scale hardware accelerator clusters to solve expensive accelerator resource management challenges

Hardware accelerators are high-cost, scarce resources in chip verification. Traditional Excel-based registration and manual coordination easily lead to device conflicts and idle resources, and lack a basis for resource assessment.

Sunrise leveraged FusionFlex to achieve online reservation, automatic scheduling, and timeout task reclamation, improving the visibility and utilization of Emulation resources. After deployment, accelerator utilization increased by 5%–10%, cross-team communication decreased by 50%, and operations efficiency improved by 20%.

06 Phytium: Platform-based upgrade of simulation regression, moving away from manual script-driven processes

As project scale expands, simulation regression faces challenges such as configuration depending on experience, opaque progress tracking, and heavy manual inspection burdens.

Phytium reused existing scripts, CI, and HPC clusters to progressively integrate X-Epic's FusionFlex, achieving task visualization, automatic error classification, automatic rerun of failed test cases, automatic waveform dump, and automatic coverage merging, while optimizing scheduling with resource data. After the transformation, manual intervention decreased by 80%–90%, debugging time was reduced by 50%, cluster utilization improved by 15%–20%, and overall regression efficiency increased by approximately 20%.

From point-level efficiency gains to full-flow collaboration, from delivering tools to delivering results, the large-scale deployment of Agentic EDA equally depends on the joint participation of users, EDA companies, and the industry ecosystem.

X-Epic will continue to be RaaS-oriented, distilling requirements, challenges, and experience from real projects into more mature product capabilities and solutions, enabling AI in chip R&D to not only "generate" but also "verify results, solve problems, and support delivery," working with industry partners to continuously advance the domestic chip design and verification ecosystem.

Original title: From Real Projects to Engineering Delivery: Six Industry Partners Discuss X-Epic Agentic EDA Practices

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