Introduction to Intel/Altera Series FPGAs

Since Altera was acquired by Intel, it seems to have abandoned the entire Chinese market, and Altera's market share has been eroded by other FPGA vendors. There are still some companies in China currently using Altera's FPGAs (mostly CPLDs), so today we will take another look at the Intel FPGA product series.

PS: Currently, the Xilinx ZYNQ series is used at a very high rate in China. In fact, the architecture of Altera's Cyclone V and Arria V SoC FPGA series, which were designed to compete with ZYNQ, was more reasonable than ZYNQ. However, circumstances create heroes—at that time Altera was busy "being" acquired, which led to the promotion of its SoC FPGA series being "strangled" by itself. As a result, very few Altera SoC FPGAs are used in China, and the corresponding documentation is scarce. The first SoC FPGA I used back then was the Cyclone V (DE1-SoC), and I had to solve all the problems myself. At that time, the only technical support available was from merchants on Taobao, and many problems could not be solved. It took me a month just to get the system running, and afterward I switched to Xilinx. Alas! It really was great!

Currently, Intel FPGAs mainly consist of 5 series: Agilex, Stratix, Arria, MAX, and Cyclone. Each series has different sub-series (which we call secondary series) for different application scenarios. Since some secondary series chips have long been discontinued, we will introduce the latest secondary series first and work backward until we reach the commonly used series.

From the above, we can simply divide them into two categories: the Agilex series is the FPGA series launched after the acquisition of Altera, while the other series are basically FPGA series from before Altera was acquired. This distinction is actually not very meaningful; I just want to say that... after the Agilex series, Altera basically disappeared from China.

From a strategic standpoint, the Intel Agilex™ FPGA family can be regarded as the competitor to the Xilinx UltraScale+ series.

The Intel Agilex™ FPGA family combines Intel 10nm SuperFin process technology, 3D heterogeneous System-in-Package (SiP) integrated with Intel's proprietary Embedded Multi-Die Interconnect Bridge (EMIB), and a chiplet-based innovative architecture to provide customized connectivity and acceleration for a variety of applications.

This new architecture supports the combination of FPGA fabric with dedicated logic blocks, such as transceivers, processor interfaces, optimized I/O, custom compute, Intel® eASIC™ devices, and many other functions, thereby creating uniquely optimized solutions for each application. Intel Agilex SoC FPGAs also integrate quad-core Arm* Cortex-A53 processors, providing a high level of system integration.

The Intel Agilex™ FPGAs are divided into the following three main series, as follows:

Intel Agilex F-series FPGAs and SoC FPGAs integrate transceivers with bandwidth up to 58 Gbps, enhanced DSP capabilities, high system integration, and the second-generation Intel Hyperflex architecture, making them suitable for a variety of applications in data centers, networking, and edge. The Intel Agilex F-series FPGA and SoC family also offers the option of integrating quad-core Arm* Cortex-A53 processors to provide a high level of system integration.

Intel Agilex I-series SoC FPGAs are optimized for high-performance processor interfaces and bandwidth-intensive applications. With Compute Express Link providing coherent connectivity to Intel Xeon processors, enhanced PCIe* Gen 5 support, and transceivers with bandwidth up to 112 Gbps, Intel Agilex I-series SoC FPGAs are ideal for applications requiring substantial interface bandwidth and high performance.

Intel Agilex M Series SoC FPGAs are optimized for compute-intensive and memory-intensive applications. Intel Agilex M Series SoC FPGAs offer coherent connectivity to Intel Xeon processors, HBM integration, enhanced DDR5 controllers, and Intel Optane DC Persistent Memory support, and are optimized for data-intensive applications requiring large amounts of memory and high bandwidth. This product family is coming soon (not yet available on the official website).

Agilex Series FPGA Naming Convention

This series is quite familiar to many, and strategically it targets Xilinx V-series FPGAs.

Device Product Family Stratix 10 Stratix V Stratix IV Stratix III Stratix II GX Stratix II Stratix GX Stratix

Launch Year 2013 2010 2008 2006 2005 2004 2003 2002

Process Technology 14 nm Tri-Gate 28 nm 40 nm 65 nm 90 nm 90 nm 130 nm 130 nm

Stratix 10 FPGA and SoC

Stratix 10 FPGA is further divided into the following series:

Stratix 10 FPGA and SoC Hard Processor System (HPS)

The Intel Stratix® 10 SoC Hard Processor System (HPS) is Intel's industry-leading third-generation HPS. Leveraging Intel's 14-nm Tri-Gate technology, Intel Stratix 10 SoC devices feature an integrated quad-core 64-bit ARM Cortex-A53, achieving twice the performance of the previous generation SoC. The HPS also enables full-system hardware virtualization by adding a system memory management unit. These architectural improvements ensure that Intel Stratix® 10 SoC will meet the requirements of current and future embedded markets, including: wireless and wireline communications, data center acceleration, and numerous military applications.

Stratix 10 FPGA Naming Convention

Stratix 10 (GX, SX, TX) Devices

Stratix 10 (MX) Devices

Stratix 10 (DX) Devices

Stratix V Series FPGAs

Intel's 28 nm Stratix® V FPGAs deliver high bandwidth and high system integration in high-end applications, offering exceptional flexibility while reducing cost and total power consumption.

Comparison with Stratix 10 as follows

Stratix V Series FPGA Selection Guide

Stratix V GT Device

Stratix V GX Device

Stratix V GS Device

Stratix V E Device

Stratix V Series FPGA Naming Convention

Although the Stratix IV series still has many applications today, we will not elaborate further here. Those interested please visit: https://www.intel.cn/content/www/cn/zh/products/details/fpga/stratix/iv.html?wapkw=stratix%20iv

From a strategic perspective, the Arria series targets Xilinx K-series FPGAs.

The Intel Arria® device family delivers the best performance and power efficiency in the mid-range market. The Intel Arria® device family features a rich set of memory, logic, and digital signal processing (DSP) blocks, along with excellent signal integrity with transceivers up to 25.78 Gbps, enabling you to integrate more functions and maximize system bandwidth. In addition, SoC products in the Arria® V and Intel® Arria® device families offer an ARM-based hard processor system (HPS), further increasing integration and saving more cost.

Families: Arria® GX, Arria® II GX, Arria® II GZ, Arria® V GX/GT/SX, Arria® V GZ, Arria® 10

Introduction year: 2007, 2009, 2010, 2011, 2012, 2013

Process technology: 90 nm, 40 nm, 40 nm, 28 nm, 28 nm, 20 nm

Arria® 10 FPGAs and SoCs

Using publicly available OpenCores designs, the core performance of Intel® Arria® 10 FPGAs is not only significantly higher than competing products, but also provides up to a 20% Fmax advantage. In addition, the Intel® Arria® 10 family offers the programmable logic industry's only 20 nm ARM*-based SoC, delivering clock frequencies up to 1.5 GHz. The Intel® Arria® 10 family also provides, for the first time in an FPGA, enhanced support for floating-point operations, taking DSP performance to a new level.

Arria® 10 FPGA and SoC Selection Guide

Arria® 10 FPGA and SoC Naming Convention

As shown in Figure 1, the enhanced ALM has 8 inputs, including a splittable look-up table (LUT), two dedicated embedded adders, and 4 dedicated registers.

Implement selected functions based on 7-input LUTs, all 6-input logic functions, and two independent functions (composed of smaller LUTs, such as two independent 4-input LUTs) to optimize core utilization. Provide 4 registers for each 8-input splittable LUT. This enables the device to maximize core performance and core logic utilization, and provides easier timing closure for register-intensive and highly pipelined designs.

Available resources per ALM: Advantage, Advantage

8-input splittable LUT: Can implement any 6-input logic function and specific 7-input functions, and can be split into smaller independent LUTs, such as two independent 4-input LUTs. Intel Quartus® design software supports splittability and is optimized for performance, efficiency, power, and area.

Two embedded adders: Support two 2-bit additions or two 3-bit additions without any additional resources. Operands can be generated from the same ALM without any additional logic.

4 registers: Optimal register-to-logic ratio to ensure the device is not register-limited. Abundant registers to improve performance for register-intensive applications or pipelined designs.

4 outputs: The inputs of a single ALM can be allocated between two output functions, supporting fast implementation of wide input functions and efficient utilization of remaining resources for narrow input functions.

MLAB: The core of Intel Stratix® series FPGAs includes a logic array block composed of regular ALMs, or configured as simple 640-bit dual-port SRAM blocks (called MLABs). MLABs can be configured as 64 x 10 or 32 x 20 simple dual-port SRAM blocks. MLABs are optimized to implement filter delay lines, small FIFO buffers, and shift registers at maximum performance with 600-MHz clock speeds.

Arria V FPGAs and SoCs

Arria V FPGA and SoC Selection Guide

Arria V FPGA and SoC Naming Convention

Arria V FPGA and SoC Summary

Intel MAX Series FPGAs/CPLDs

The Intel MAX series FPGAs/FPGAs strategically target Xilinx's CPLD series.

This series was originally Altera's CPLD series, but Intel subsequently changed these, renaming CPLDs as FPGAs (small-sized). This change may represent the future development of CPLDs (CPLDs may no longer exist in the future market).

This series still has CPLD as its main architecture, but its internal structure is still FPGA, so it cannot be called CPLD; it is more like CPLD+FPGA. Intel still promotes this series as CPLDs during marketing.

Therefore, it is necessary to introduce this in two separate series here.

Series Mature CPLD family MAX® II CPLD MAX® IIZ CPLD MAX® V CPLD Intel® MAX® 10 FPGA

Introduction year 1995 - 2002 2004 2007 2010

Process technology 0.50-0.30 micron 180 nm 180 nm 180 nm

Key features 5.0 V I/O Higher I/O count Low static power consumption Low cost, low power

Intel MAX 10 Series FPGA

Intel MAX 10 FPGAs increase the integration of external system component functions, thereby reducing system-level costs. Unlike CPLDs, 55 nm Intel MAX 10 FPGAs include the full range of FPGA capabilities, such as digital signal processing (DSP), analog blocks with analog-to-digital converters (ADC) and temperature sensors, embedded soft-core processor support, memory controllers, and dual configuration flash memory.

Intel MAX 10 Series FPGA selection guide

Intel MAX 10 Series FPGA naming convention

Intel MAX V Series CPLD

Delivering low cost, low power, and on-chip features, MAX® V CPLDs are the most valuable devices on the market. MAX® V devices use a unique non-volatile architecture to deliver reliable new features with total power consumption up to 50% lower than competing CPLDs. MAX® V devices are ideal for general-purpose and power- and space-constrained designs across many market segments, including wireline, wireless, industrial, consumer, computer and storage, as well as broadcast and military. MAX® V CPLDs are used in a wide variety of applications that previously could only be implemented in previous-generation ASICs, ASSPs, FPGAs, and discrete logic devices.

Intel MAX V Series CPLD selection reference

Intel MAX V Series CPLD naming convention

Intel Cyclone Series FPGA

Strategically, this series should be positioned against the Xilinx S series.

This series of FPGAs should be the most familiar to everyone; it is the series that Altera promoted in China. Many university course design projects use Altera Cyclone series FPGAs, and for many people, their first introduction to FPGAs was likely this series (many development boards use this series of FPGAs), so there is no need to say much about the documentation.

Here is a brief introduction to Cyclone 10, Cyclone V, and Cyclone IV (brief introduction).

FPGA Cyclone® FPGA Cyclone® II FPGA Cyclone® III FPGA Cyclone® IV FPGA Cyclone® V FPGA Cyclone® 10 FPGA

Introduction year 2002 2004 2007 2009 2011 2017

Recommended for new designs No No No Yes Yes Yes

Intel Cyclone 10 Series FPGA