Anlogic Phoenix Series Ramp-Up Shows Domestic FPGA's Path to High-End

A noteworthy shift is emerging in the domestic FPGA market: in the past, domestic vendors mostly relied on mature process nodes and mid-to-low-end products to enter the market and address customers' localization needs; today, as demand grows in industrial control, data centers, AI infrastructure and other markets, and as delivery cycles of international FPGA vendors lengthen, domestic FPGA vendors are beginning to gain more opportunities to enter mid-to-high-end applications.

Anlogic's recent business performance is a microcosm of this shift.

The latest financial report shows that in the first three quarters of 2026, Anlogic achieved operating revenue of RMB 737 million, up 100.07% year on year; third-quarter revenue alone reached RMB 305 million, up 110.49% year on year. More notably, the company explicitly stated in its earnings forecast that the rising revenue share of Phoenix Series FPGA products is driving continuous optimization of its product mix. In other words, this round of growth is not just a recovery in market demand and higher shipments, but is accompanied by changes in product mix.

From revenue growth and product mix optimization to capital investment, Anlogic is entering a new stage of development. For the domestic FPGA industry, the more worthwhile question behind this is: as domestic vendors are no longer satisfied with substitution opportunities in mature markets and begin to move toward larger-scale, higher-performance FPGA markets, what technical and industrial thresholds must they cross? And how does Anlogic plan to forge its own path to high-end?

I. Behind the Doubling of Revenue: Phoenix Series Is Becoming a New Growth Pillar

Looking only at revenue figures, Anlogic's 100.07% year-on-year growth in the first three quarters is already quite outstanding. But for an FPGA company, the quality of revenue growth is often more noteworthy than the growth rate itself.

As we all know, FPGA products have a long customer adoption cycle. When selecting devices, customers consider not only chip logic capacity, interface resources, power consumption and price, but also design tools, IP resources, development difficulty, long-term supply and product reliability. Once a device enters a customer's product design and completes verification, it is usually not easily replaced. Therefore, revenue growth for FPGA vendors depends both on market demand and on whether products can enter customer projects and continue to ramp up.

In Anlogic's latest performance growth, the most noteworthy point is that data centers have become a new source of growth. The company explicitly stated in its earnings forecast that rapidly growing demand for data center infrastructure has driven a significant increase in shipments of related products. Also noteworthy is the rising revenue share of Phoenix Series products.

The Phoenix Series is Anlogic's product line positioned for high-performance applications. The rising sales share means the company is extending from a market structure previously dominated by mature-node products and broad application coverage toward higher-performance products and higher-value applications. This change does not mean mature products have lost importance; rather, it shows that Anlogic's product matrix is beginning to develop new growth pillars.

Recently, the author interviewed Xie Ding, Deputy General Manager of Anlogic. Xie Ding revealed that the company's product strategy for the next three to five years will advance along two main lines: one is to break through toward the high end, adopting more advanced processes to develop FPGAs with larger logic capacity, supported by higher-spec hard IP and higher-bandwidth interfaces; the other is to continue improving the product matrix on mature process nodes the company has already mastered, consolidate existing markets and expand into more segmented application areas.

Xie Ding summarized these two paths as a "two-pronged approach": "Both lines are main lines for us; it is equivalent to grasping both hands, and both hands must be strong."

From this perspective, the significance of the rising sales share of the Phoenix Series is not merely that more high-performance chips have been sold, but that Anlogic is gradually building a product structure covering different performance tiers and different application markets. For domestic FPGA vendors, this is more important than simply pursuing parameter breakthroughs in a single product.

II. High-End FPGA Is Not a Parameter Race, but Complete System Capability

For domestic FPGAs to move toward the high-end market, the first question to answer is: what kind of FPGA counts as high-end?

Xie Ding has a relatively clear judgment: "In fact, there is no single quantitative indicator; it depends on the overall software and hardware system delivery capability." He further explained that high-end FPGAs first require advanced processes and larger logic capacity, along with matching hard IP, high-speed interfaces and memory bandwidth; on this basis, EDA software must be capable of handling high-speed, high-performance architectures and ultra-large-scale designs, and must also be supported by corresponding IP, ecosystem solutions, as well as volume manufacturing engineering and packaging and testing capabilities.

Xie Ding emphasized that raising a few metrics to high levels cannot be called a high-end breakthrough. "Putting a few metrics on a pedestal actually has little industrial practical value." A true breakthrough means going beyond hardware specifications to solve problems across software and hardware, system solutions, and customer engineering applications.

He noted that Anlogic has persisted in forward-looking R&D over the years. After new hardware products are launched, the software, IP, and the entire ecosystem still need to be gradually refined through continuous engineering iterations with customers. Only when these elements truly work in concert can products be deployed in real projects.

Therefore, the high-endization of domestic FPGAs is not a single-point breakthrough but an overall improvement in system capabilities. Chip design capability, EDA tool capability, IP ecosystem, and customer engineering experience are all indispensable.

III. Phoenix Second Generation: From Larger Logic Scale to Higher Bandwidth and Chiplet

Having clarified the systemic requirements for high-end FPGAs, Anlogic's next product roadmap has a clearer direction. Xie Ding introduced that Anlogic's next-generation higher-end products will still be based on the Phoenix architecture, namely the Phoenix architecture second generation currently under development. Compared with existing products, the next-generation products will achieve significant improvements in logic capacity, high-speed interfaces, and bandwidth, while beginning to involve Chiplet technology.

According to Xie Ding, the PH series products in the existing Phoenix lineup already feature 500K-level logic capacity, support DDR4 and DDR5 2800 through HPIO multiplexing, provide dual-channel 64-bit memory interfaces, and support approximately 100G Ethernet and PCIe 4.0 interface capabilities.

On this basis, the Phoenix second generation plans to double its logic capacity, SERDES, and bandwidth metrics. It should be noted that these are R&D plans for next-generation products, not specifications of products currently in mass production.

Notably, Anlogic is also beginning to consider Chiplet technology in its next-generation products. From Xie Ding's introduction, Anlogic's thinking about future high-end FPGA architectures is not merely following the traditional path of continuously scaling up single-chip size, but rather evaluating architecture directions better suited to future high-performance requirements — the next-generation Phoenix products will further strengthen features related to AI and data center applications on the basis of larger logic scale and higher bandwidth, while exploring technology directions such as Chiplet.

In Xie Ding's view, FPGAs should better leverage their advantages in logic programmability, high-bandwidth interfaces, and hardware data processing, rather than simply competing with GPUs on general-purpose computing power.

However, high-end product development is not simply about pursuing the most advanced process. Xie Ding believes that process selection requires comprehensive consideration of R&D investment, process stability, and product cost-effectiveness. For FPGAs — products with long lifecycles and long customer adoption cycles — the most advanced process node is not necessarily the best; long-term supply and industry chain support must also be considered. He mentioned that 12nm to 16nm remains a realistically attractive process range currently, and Anlogic will advance gradually according to its own R&D capabilities and industry chain conditions, rather than blindly leaping forward in pursuit of advanced processes.

IV. AI Data Centers: FPGA Is Not a GPU Replacement but an Important Collaborator in Computing Systems

The rapid development of AI computing infrastructure has brought new market opportunities for FPGAs. But in this market, what role can FPGAs actually play? Do they have the opportunity to become an important computing option beyond GPUs?

Xie Ding summarized FPGA opportunities in AI data centers into three directions: data switching and co-processing, server companion chips, and AI inference.

The first path is the extension of traditional FPGA capabilities into data centers. Such applications share some similarity with the traditional role of FPGAs in communication equipment: the core is not general-purpose computing, but high-speed data switching, protocol processing, data preprocessing, and cache management.

Xie Ding gave an example during the interview: in some rack-level system architectures for AI inference, FPGAs are used to handle data switching and auxiliary processing tasks. This case at least demonstrates that in AI computing systems, FPGAs do not necessarily need to directly perform model computation — they can also play a role as system-level data processing and interconnect components.

The second path is companion chips in servers. This may be a relatively certain category of market opportunity for Anlogic at present.

Xie Ding explained that in an AI server rack, in addition to main compute chips such as GPUs and CPUs, a large number of small-scale FPGAs are needed to handle various system control tasks. Based on his observations, a single rack may use hundreds of FPGAs with small to medium-scale logic cells, with applications covering root of trust, power sequencing management, voltage conversion, fan management, storage backplane management, and BMC-related security interfaces.

These tasks may not appear complex, but they have distinctly differentiated characteristics: different devices require different control logic, functions are dispersed, requirements are diverse, and it is often unnecessary to develop a separate ASIC for each function. FPGAs can quickly adapt to different designs through programmable logic, offering high flexibility.

The value of this type of application lies not in how large the logic scale of a single chip is, but in the fact that as server and rack scales continue to expand, the demand for accompanying chips will increase accordingly.

Xie Ding revealed that Anlogic's EF5 series has already achieved volume adoption with leading server customers, with shipments in the data center sector increasing significantly. As the number of projects grows, future shipment volumes are expected to rise further.

The third path, which is also a direction frequently discussed in the industry, is using FPGAs for AI inference.

Xie Ding believes that AI inference can be further divided into two stages: Prefill and Decode. The Prefill stage requires parallel processing of input prompts and context, with high computational intensity, where GPUs still hold a clear advantage. In the Decode stage, the model generates tokens one by one, requiring continuous access to model parameters and previously generated information. This is a memory-access-intensive task, and the importance of storage interface bandwidth increases accordingly.

From this perspective, the computational characteristics of the Decode stage differ from those of Prefill. FPGAs can flexibly configure compute resources and memory bandwidth based on specific models and application requirements, and explore hardware implementations better suited to specific inference tasks through mixed-precision computing approaches.

He revealed that Anlogic is currently conducting relevant validation with partners, using 400K and 500K-class products for inference application exploration. Next-generation products will also be further optimized in areas such as memory bandwidth and compute density to better meet related requirements.

It should be emphasized here that FPGAs are not intended to replace GPUs, CPUs, or NPUs. Xie Ding believes that data switching, co-processing, and server companion chips all essentially work in coordination with CPUs and GPUs; even in the inference domain, FPGAs merely provide an alternative implementation approach for specific computational stages and application requirements.

"The real opportunity that AI data centers bring to FPGAs is to re-enter more complex compute systems and find new value positions in data switching, system control, storage access, and specific inference tasks," he emphasized.

V. EDA and IP Ecosystem: Determining Whether FPGAs Can Move from Chip Sales to Scale Applications

If chip hardware determines how many resources an FPGA can provide, then EDA tools and the IP ecosystem determine whether customers can efficiently use these resources.

For domestic FPGA vendors, this is also a threshold that must be crossed.

In the interview, Xie Ding noted that EDA tools are both a technical barrier and a moat in long-term competition for FPGA vendors. He believes that Anlogic's software has evolved from "usable" to "easy to use." According to his account, over the past year or more, Anlogic has made notable progress in software stability and design convergence capability, and tool blockage issues encountered by customers in actual projects have become relatively rare.

He specifically mentioned that Anlogic's software, within the product specifications it can offer, is already able to well support customers in completing design and implementation, and software is no longer a major obstacle to project progress. Next, as high-capacity, high-performance products continue to be introduced, EDA tools will continue to iterate and upgrade.

At the same time, AI agents are also changing the way FPGAs are developed.

Xie Ding believes that large models will significantly lower the barrier to FPGA application development and improve project convergence efficiency. Anlogic is developing its own EDA Agent, hoping to enable mainstream AI tools to invoke Anlogic's EDA tools by providing MCP services along with well-developed Skills and underlying tool interfaces.

Beyond EDA, the IP ecosystem is also a key investment area for Anlogic in the next stage. He stated that Anlogic has accumulated more than 200 application IPs and reference solutions and is continuously expanding them. Xie Ding introduced that the company is building dedicated teams around basic interfaces, wired Ethernet, wireless algorithms, video interfaces, industrial control, SoC buses, and AI computing power to improve IP resources across different domains.

6. Domestic FPGA Competition Enters a New Stage: Differentiation Matters More Than Simple Substitution

In recent years, the important task for domestic FPGA vendors has been to enter customer supply chains and address localization and supply security concerns. However, as the number of local vendors increases and product portfolios gradually mature, competition is shifting from "can it substitute" to "why should it be chosen."

In 2026, extended lead times and tight supply for some products from international FPGA vendors have created a clear market window for domestic vendors. Many customers have begun re-evaluating their supply chains and accelerating the adoption of domestic FPGAs.

But Xie Ding also believes that the supply chain window is only an opportunity and cannot be the sole reliance for the long-term development of domestic FPGAs. For the high-end market, Anlogic hopes to maintain close communication with leading customers in key industries while covering general specifications, providing differentiated products around customers' actual pain points rather than simply replicating the specifications of international vendors.

"As latecomers, domestic vendors must certainly offer differentiated competitive advantages rather than engage in simple homogeneous substitution."

This is also why Anlogic emphasizes scenario-based product definition. Xie Ding made it clear that Anlogic's competitiveness comes more from independent R&D, product quality, stable supply, scenario-based customization, and technical support for domestic customers.

Looking at Anlogic's product roadmap, the company has not set high-end product development against mature market operations. Instead, it aims to maintain market coverage and customer base through mature-node products, advance into higher-performance markets through the Phoenix series, and complete the overall product system with EDA, IP, and application solutions.

This also means that competition in domestic FPGAs is entering a new stage. In the past, the competition was about who could build chips and who could enter customer supply chains; in the future, the competition will be about whether products can continuously iterate, whether toolchains are mature, whether the IP ecosystem is complete, and whether differentiated value can be created around customers' real applications.

Anlogic is attempting to forge a path that balances mature markets with high-end breakthroughs. It may not be the fastest path, but for an industry like FPGAs with high R&D investment, long verification cycles, and long product life cycles, truly valuable progress must ultimately be reflected in customers' sustained use, stable product shipments, and the ability of the company to establish sustainable commercial returns. (End)