Why Your FPGA Design Might Need a Softcore Processor – What are the Options? (Adam Taylor, EOC 2022)

According to the talk, what is the primary reason to replace a large, complex finite state machine (FSM) in an FPGA with a soft-core processor?

What key trade-off does Adam Taylor highlight when choosing a soft-core processor implemented in FPGA fabric versus a hard-core processor on a SoC?

For small MCU-like soft cores inside an FPGA, which boot/run memory approach does the speaker recommend as the simplest and why?

Which AXI VALID/READY handshaking rule did the speaker warn is critical to avoid deadlock in AXI designs?

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Firmware Co-Design & Development for IP Cores in C++/SystemC using Verilator

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