Turning Python directly into synthesizable FPGA firmware has already been demonstrated running in a browser. After comparing median-filter implementations built with MyHDL, Christopher Felton argues that Vivado C HLS offers little benefit over HDL-level descriptions, and that the hard part is always algorithm selection, not the language.
Martin Strubel described using yosys and its Python API to directly build synthesizable primitives, inspect schematics, and generate post-synthesis Verilog or firmware, skipping the long MyHDL or nMigen-to-Verilog/VHDL conversion chain. The official claim is roughly five seconds from browser to FPGA. MyHDL is also now available on EDAPlayground, with a two-panel editor placing the testbench on the left and the HDL under test on the right, allowing Python HDL verification to run directly. This means the barrier to entry is dropping, but the five-second figure is a claim made in a toolchain demo scenario; real projects still depend on design size and constraint complexity.
Christopher Felton compared a Vivado HLS median-filter example with a MyHDL RTL implementation and concluded that C-to-gate HLS offers almost no practical benefit. His reasoning is that the test mixes language paradigms with abstraction levels: Vivado C HLS is imperative and step-by-step, while MyHDL provides concurrent, HDL-level descriptions while retaining Python readability and elaboration features. He acknowledges that people familiar only with C may find C-HLS helpful, but that large-scale parallel FPGA work is better served by non-C tools. The real issue is that HLS does not replace understanding of the hardware; choosing the right algorithm is the hard part.
In MyHDL's first year as a Google Summer of Code sub-organization, Christopher Felton reviewed the process from selecting two students to delivering SDRAM and conversion work, noting proposal expectations, the value of early patches, and the need for frequent mentoring and flexible milestones. Sriyash Caculo implemented MyHDL digital filter modules during GSoC and integrated them with pyFDA, aiming to convert pyFDA's floating-point designs into fixed-point MyHDL modules, automatically generate VHDL or Verilog, and provide tests and tutorials. The value of this work is not in the promotional language but in making the conversion step from filter design to hardware a reusable flow.
For engineers in China working on high-speed interfaces and board design, this flow will not replace vendor toolchains in the short term: synthesis, timing closure, and bitstream generation still have to go through Vivado or Quartus, and MyHDL generates Verilog/VHDL that then enters the vendor flow. What is worth watching is the verification stage; Python HDL simulation on EDAPlayground is suitable for quickly validating algorithm ideas, and the pyFDA-to-MyHDL fixed-point conversion path has reference value for early exploration of filter IP. If a team already has a C-HLS flow, Felton's comparison shows it does not necessarily bring area or cycle advantages, and microarchitecture control should remain the basis for tool selection.