gol-hotstate — Conway's Game of Life on the Hotstate Machine
Conway's Game of Life (rule B3/S23), running entirely as compiled Hotstate microcode, rendered live to a 1.14" ST7789 SPI LCD. Verified end-to-end against a canonical B3/S23 software oracle and flashed to a real Sipeed Tang Nano 9K .
A 32×32 toroidal grid of cells lives in two double-buffered writable BRAMs. Each generation, every cell's 8 Moore neighbors are summed (wrapping at the edges), the next state is looked up in a 2×9 const-ROM ( rule[alive][count] ), and only the cells that actually changed are blitted to the LCD as 4×4 pixel blocks — so a mostly-empty field with a few gliders costs only a handful of SPI writes per generation, not a full-screen redraw.
A physical button (S2, board pin 3) toggles between two seed patterns — a single glider (glides forever, useful as a "is this actually running" sanity check) and a four-glider pattern (settles into a mix of still lifes and oscillators after some generations, which is genuine B3/S23 behavior of that seed, not a bug) — wiping the screen and restarting the CA on each press.
Building and running
The gol_template.v / .mem / .vh / .toml files in this directory are hotc's compiled OUTPUT from gol.c + lcd_driver.c ( gol.c passed first on the hotc command line, since hotc names the generated module/files after the first input file's basename — gol , not lcd_driver ), checked in as-is. This repo doesn't ship hotc itself, so there's no generate step — the commands below just build and flash what's here:
# Verilator RTL simulation (free-running trace capture, not self-checking) make hw_sim # Synthesize + place-and-route + pack a bitstream for the Tang Nano 9K make synth pnr pack # Program a connected Tang Nano 9K over USB make prog Hardware target Sipeed Tang Nano 9K (Gowin GW1NR-LV9QN88PC6/I5), pinned out in lcd114.cst :
top.v inverts both active-low board inputs ( rst = ~resetn , mode_btn = ~mode_btn_n ) before wiring them into the gol hotstate instance; everything else ( sclk , mosi , cs_n , dc , lcd_resetn ) maps straight through to the ST7789 panel.
Device usage (GW1NR-LV9QN88PC6/I5)
Measured 2026-09-22 from nextpnr-himbaechel 's own post-route report, on the bitstream that runs on the board. Zero-use resource classes omitted.
BSRAM is the binding resource at 50% — the two grid generations plus the microcode and variable tables. Logic is nowhere near full: a design twice this size would still fit the LUT budget but would not fit the block RAM.
Timing: post-route Fmax 59.72 MHz on inst_gol.clk , against the 27 MHz board oscillator the design actually runs at — roughly 2.2x margin. (nextpnr reports "PASS at 12.00 MHz"; 12 MHz is just its default target for an unconstrained clock, not a requirement of this design.)
Unlike the Tang Nano 20K examples in this repo, this flow does not pass -noalu — hence the 304 ALU cells. The apicula ALU miscompute ( YosysHQ/apicula#514 ) is specific to the GW2A-18C; the GW1N-9C is unaffected.
Toolchain for these numbers: yosys 0.69+62, nextpnr-himbaechel 0.11.1-26, gowin_pack . Unlike KAN_hotstate on the 20K, gol-hotstate synthesizes and runs correctly on yosys 0.69 — that problem is design- and device-specific.
Algorithm ( gol.c )