The hardware bottleneck in edge video AI is often not peak compute, but how memory bandwidth is allocated. The Fudan Microelectronics FMQL100TAI development kit completely separates the PS and PL DDR3, with 1GB on the PS side and 2GB on the PL side. This seemingly simple isolation determines whether a high-frame-rate video pipeline will compete for bandwidth between the ARM and the FPGA.
The core board uses four ARM Cortex-A53 cores at 1GHz, with 1GB DDR3 independently allocated on the PS side; the PL side has 444K logic cells and 2GB DDR3 independently allocated. The two memory sets each use their own channels, so when video data is preprocessed and buffered on the PL side, it will not squeeze the bandwidth the ARM uses to run the operating system. The PL side also exposes 212 HR IOs and 150 HP IOs, with independent 50MHz and 100MHz PL clocks. This means that for high-resolution industrial vision, the risk of frame drops is reduced at the architecture level rather than being rescued by software scheduling.
The core board integrates 16 GTX high-speed transceivers, and the carrier board converts these lanes into dual 10G SFP+ optical ports, SDI input, HDMI output, an RGB+I2C touchscreen interface, as well as PCIe, RapidIO, SATA, Gigabit LAN, and USB. The inclusion of SDI is a real convenience for industrial vision scenarios, while the 10G optical ports target ultra-high-definition video backhaul and high-throughput traffic. High-speed lanes are generously reserved, but few engineering projects actually use all 16 GTX lanes, so channel count must be calculated against the actual number of peripherals during selection.
The kit includes an adapter baseboard that allows two boards to interconnect via PCIe, operating in RT and EP modes respectively, and also supports RapidIO interconnection; the vendor says low-level DMA transfer examples are already written. The carrier board also provides a standard FMC interface with GTX and User IO, which can connect high-speed AD/DA daughter cards or custom optical/electrical modules. What must be budgeted in advance is the emulator: Fudan Microelectronics FPGAs are not compatible with ordinary downloaders and require I-JET, with one programming cable each for the PS side and the PL side. Engineers accustomed to the Xilinx platform who miss this purchase at project initiation will find development blocked outright.
For domestic engineers working on high-speed interfaces and boards, the reference value of this kit lies in its architecture rather than compute figures: the PS/PL memory decoupling approach can be carried directly into their own carrier board designs, and the dual 10G optical ports and PCIe RT/EP cascading also save preliminary work on high-speed board timing debugging. But the toolchain is a hard barrier: the I-JET emulator is not on the compatibility list of ordinary downloaders, so if a team is migrating from the Xilinx platform, the procurement list and training plan must be adjusted accordingly. The vendor claims 27.52TOPS@INT8; with AI compute and both 10G optical ports fully loaded, the core board heats up noticeably, so structural design needs to leave thermal headroom.