Gowin's toolchain hides an easy-to-use and reasonably capable on-chip logic analyzer, but its rules of use are stricter than one might imagine: only one GAO configuration file can be active at any given time. For engineers accustomed to open-source simulation flows, this is both a convenience and a constraint.
After creating a GAO configuration file in the GOWIN tools, the tool builds a logic analyzer into the design, and the configuration file itself sets the trigger conditions. The editor offers several options; when creating from scratch, it asks whether to use Lite mode; according to the original text, standard mode is the conventional choice, while RTL mode mainly displays symbols defined by the designer rather than symbols added during processing. This means the debug logic is synthesized into the chip along with the design, and the probes and trigger conditions are determined at build time rather than attached temporarily after board bring-up.
Only one GAO file can be active at a time. The method given in the original text is to right-click the file in the IDE's Design tab to disable it; the file is marked with a red X and excluded from subsequent builds, and re-enabling it restores it. This allows switching among multiple GAO files, or even multiple Verilog files, between builds—for example, one for test and one for production. The real problem is that this switching is done manually via right-click, multiple probe configurations cannot coexist in the same build, and the debug plan needs to be arranged in advance.
The original text presents two debug scenarios: on the left, a toggling LED pulse, which is tricky because the sampling clock is 27 MHz; on the right, serial data, using a slower clock dedicated to debugging. Both scenarios point to the same thing—the choice of sampling clock directly determines what can be seen. High-speed signals require a sufficiently fast sampling rate, while slow serial data is instead suited to a slower clock to extend the observation window. This means the logic analyzer configuration is not set once and universally applicable; it must be adjusted according to the signal under test.
For engineers using Tang Nano 20K and the Gowin toolchain, the practical significance of this flow is: an on-chip logic analyzer can eliminate the need for external probes, but configuration management must be incorporated into version control habits; test and production builds are distinguished by manually disabling files, which is error-prone. Open-source simulation flows still bear the primary verification responsibility before build, and GAO is more of a supplementary means after board bring-up. If a project relies on multiple probe configurations in parallel, the build matrix needs to be planned in advance; the toolchain itself provides no coexistence mechanism, and this will be amplified in team collaboration.