As edge devices connect an increasing number of components and sensors, market demand continues to grow for devices that securely and efficiently process large volumes of data. AMD's newly introduced Spartan UltraScale+ XA FPGAs combine cost optimization with high I/O advantages, helping automotive designers quickly address challenges by building camera and LiDAR systems with low cost, high energy efficiency, and modern security features.
High I/O and low power: Delivers a high I/O-to-logic cell ratio1; built on a 16nm FinFET process, reducing total power consumption by 30% compared to the previous generation2.
Supports high-speed data transmission: The XASU35P supports MIPI D-PHY with lane rates up to 2.5 Gb/s, meeting the data rates required for point cloud generation.
Mature design tools: The powerful, high-quality AMD Vivado Design Suite, introduced in 2012; covers all stages from simulation to verification and supports multiple FPGAs.
Long-term supply and upgrade support: AMD has been deeply engaged in the FPGA business for nearly 40 years, with billions of devices shipped; product lifecycles exceeding 15 years and field upgradability help extend design longevity.
1. The conclusion of "ultra-high I/O-to-logic cell ratio" is based on internal analysis conducted by AMD. This analysis evaluated the I/O-to-logic cell ratio of 28nm and below FPGAs based on published product datasheets of the AMD Spartan UltraScale+ SU10P FPGA and comparable products. Cost savings per I/O bank were calculated based on February 2024 list prices of the AMD Spartan UltraScale+ SU10P and AMD Spartan 7 7S50, for user designs requiring at least 200 general-purpose I/O (GPIO). (SUS-011)
2. Projections are based on AMD internal analysis in January 2024, calculating total power (static and dynamic) based on logic cell count differences of the AMD Artix UltraScale+ AU7P FPGA, using the Xilinx Power Estimator (XPE) tool (version 2023.1.2). Estimated total power may differ from actual total power after final product availability, depending on configuration, design, usage, and other factors. (SUS-003)
Original title: Automotive-Grade AMD Spartan™ UltraScale+™ XA FPGAs: Balancing High I/O, Low Power, and Long-Term Reliability
2026 In-Depth Analysis: AMD FPGA Board Development Customization Service Providers — Core Capabilities and Mainstream Solution Comparison
AMD Launches Automotive-Grade Spartan UltraScale+ XASU35P FPGA
UltraScale+ Board Hands-On: The 4 Most Memorable Points to Save Half the Detours
eMMC as an Auxiliary Boot Device in AMD Zynq UltraScale+ MPSoC Architecture

Example of Using the Vision Library L1 Remap Function in AMD Zynq UltraScale+ Bare-Metal Design

Second-Generation AMD Kintex UltraScale+ FPGAs Optimize Next-Generation AV and Media Workflows

AMD Spartan FPGA Upgrade: Bigger, Smarter, More Scalable, More Secure

Detailed Explanation of the Interrupt Architecture of AMD Zynq UltraScale+ MPSoC

AMD Zynq UltraScale+ RFSoC Evaluation Kit Debug Checklist

Highlights of Second-Generation AMD Kintex UltraScale+ FPGAs
AMD Launches Second-Generation Kintex UltraScale+ Mid-Range FPGAs to Power Intelligent High-Performance Systems
[ALINX Selection Guide] Quick Selection of AMD Kintex UltraScale+ Series FPGA Development Boards
Implementing Interconnection Between AMD UltraScale+ FPGAs and AMD Versal Adaptive SoCs Using the Aurora 64b/66b Protocol
AMD UltraScale Architecture: A Technical Analysis of High-Performance FPGAs and SoCs
Now Available: AMD Spartan UltraScale+ FPGA SCU35 Evaluation Kit — An Affordable Platform for All Developers