This event session is presented by Olivia Wu, Distinguished Engineer at Meta.
AI model architectures are evolving faster than traditional chip development cycles, and at Meta's scale-serving billions of users across ranking and recommendation and generative AI workloads-this mismatch is untenable. Meta's Infra Silicon team has responded with a six-month SoC tape-out cadence, delivering four successive MTIA generations targeting workload profiles from R&R training to large-scale GenAI inference.
Achieving this velocity while meeting hyperscale reliability requirements demands a fundamentally different methodology. Chiplet-based SoC architecture is the enabler: decomposing systems into modular die allows new process nodes and capabilities-enhanced HBM bandwidth, MX4 precision for Mixture-of-Experts, die-to-die interconnects-to be introduced incrementally while reusing proven IP across generations.
Chiplet composability goes further, enabling validated die to be repackaged alongside new or existing chiplets to rapidly form differentiated products that address shifting model architectures without respinning silicon end-to-end. This talk illustrates how Meta employed chiplet methodology across its MTIA family, the velocity and reuse benefits gained, and how Meta addresses the complexity of bringing modular silicon to hyperscale production.