A domestic FPGA vendor put its design toolchain on display at a specialty electronics exhibition. At the Shanghai New International Expo Centre on November 10, CASIC Yihaiwei exhibited high-reliability FPGAs, SiPs and sensing-control SoCs, claiming its in-house Yilingxi suite covers the full flow from synthesis to bitstream generation. For engineers building specialty boards, the key question is not just device availability but whether the toolchain can truly replace external dependencies.
At the 2026 Autumn National (Shanghai) Specialty Electronic Components Exhibition, CASIC Yihaiwei displayed its Yihai Shenzhen® and Yihai Longzhu® series high-reliability FPGAs, officially described as integrating high-speed interconnect, large-capacity DSP and memory resources. Also on show were SiP system-level chips integrating multiple functional dies, positioned around compact size and controllable power consumption; and an intelligent sensing-control SoC combining multiple compute engines with dedicated functional units. Supporting reference designs and evaluation boards for fiber-optic gyroscope signal processing, real-time control and high-speed data acquisition were exhibited alongside. The product line extends from devices to board-level solutions, aimed at letting customers evaluate with a board in hand rather than just a datasheet.
The other item worth examining at the booth is the Yilingxi® design suite. The vendor claims it covers the full flow from RTL synthesis and place-and-route to bitstream generation, and can shed dependence on external tools. For specialty board design, that statement carries more weight than any single device parameter: a toolchain cutoff means existing designs cannot be recompiled, and supply-chain security becomes moot. The real question is that full-flow self-development only shows the chain is closed, not that timing closure quality, IP maturity and migration cost for existing projects have passed muster. The vendor did not provide these metrics in its materials; engineers need to verify them with their own designs.
Visitors on the first day included research institutes, system integrators and component procurement leads. According to the materials, visiting experts focused on reliability metrics, batch consistency, delivery assurance and supporting technical services for domestic FPGAs in specialty scenarios, and discussed device selection, environmental adaptation and system integration; for miniaturized system requirements they explored joint development and solution adaptation. These questions point to the same thing: procurement decisions in specialty scenarios are not based on performance alone, and batch consistency and long-term supply capability are often veto factors. The vendor steering customization requests toward joint development indicates that adaptation work remains between standard products and project requirements.
For domestic teams building specialty boards, the direct value of this news is an additional candidate with an in-house toolchain on the selection list. For existing designs considering migration, validate timing closure and IP availability in small batches first, then discuss volume replacement; evaluation boards and reference designs can shorten early validation, but loop metrics in scenarios such as fiber-optic gyroscopes and real-time control still need in-house testing. On the supply-chain side, the full-chain domestic claim currently comes from the vendor's own account; actual capacity and lead times for wafer fabrication, packaging and testing were not disclosed, and buyers should write batch consistency into acceptance criteria rather than judging by booth demos.