Beginner Academy
A 100-Day Roadmap for FPGA Beginners
Fig. A 100-Day Roadmap for FPGA Beginners · themed illustration
The biggest trap in FPGA learning is not “difficulty” but “not knowing what to do next.” This roadmap splits 100 days into four phases, each with a verifiable deliverable — finish one, then move to the next, without anxiety.
| Phase | Content | Verifiable deliverable |
|---|---|---|
| Phase 1 Weeks 1–2 |
Digital circuit fundamentals (AND/OR/NOT gates, flip-flops, combinational/sequential logic) + Verilog basics (module, always, assign, blocking/non-blocking assignment) | Write a counter and a finite state machine (FSM) and pass simulation |
| Phase 2 Weeks 3–6 |
Buy an entry-level dev board (¥100–300 is enough to start; domestic entry boards offer great value), build an LED chaser, key debounce, seven-segment display, UART loopback | UART TX/RX working: PC sends data, the board echoes it back |
| Phase 3 Weeks 7–10 |
Verification and debugging basics: writing simulation stimulus, timing constraints (clock constraints), ILA/ChipScope on-chip debugging, reading timing reports | Debug a “simulates fine, board doesn’t light up” case to correctness and write up the cause |
| Phase 4 Weeks 11–14 |
Into the open-source ecosystem: Verilator for simulation, Yosys/nextpnr for open synthesis and place & route, LiteX for SoC; join a competition or maintain a small project | Open-source a complete small project on GitHub (with README and simulation) |
Three Key Suggestions
- Simulate first, board later: 90% of logic errors should surface in simulation. Simulation is free, fast, and repeatable — the lowest-cost verification method.
- Treat “board doesn’t light up” as your best teacher: debugging is a core FPGA engineer skill. For every failure, record three things — symptom, hypothesis, verification method.
- Get into open-source communities early: Verilator, Yosys, LiteX, and OSVVM are active projects; reading their docs and issues grows you faster than secondhand tutorials.
Resources (by Priority)
- Official docs and examples: your board vendor’s example library (top priority);
- Open-source tutorials: Verilog style guides, Verilator docs, Yosys docs;
- Communities: FPGA forums and competition communities, FPGA collection repos on GitHub;
- This issue’s “Open Source Workshop” column launches with this issue and will break down Verilator / Yosys / LiteX hands-on issue by issue.