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AXU5EVB-P AMD SoC Development Board
Key specifications
| Model | AXU5EVB-P |
| Device | XCZU5EV |
| Family | AMD SoC Development Board |
| Memory (DDR) | PS: 4 GB DDR4 (4 x 1 GB, 64-bit, 2400 Mbps); PL: 1 GB DDR4 (1 x 1 GB, 16-bit, 2400 Mbps) |
| Official list price | CNY 8599.00 |
Field values are parsed from the official ALINX product page (spec sheet updated 2026-11-04). Untranslatable Chinese descriptions are omitted rather than machine-translated.
PCIe capability
The official page states the interface in Chinese; the verbatim wording is shown on the Chinese version of this board page rather than machine-translated here.
Structured reading: PCIe Gen3 x2; 8 GT/s per lane; expansion slot (PL side); GTY transceivers in PL.
Verdict (compiled by fpga.love): Usable as a PCIe accelerator card: PL GT transceivers present, PCIe exposed on an expansion slot.
Other boards in the same family
Source of record (official ALINX product pages, Chinese, with the full interface list and documentation): https://www.alinx.com/detail/224
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