xclbin生成时无法禁用phys_opt_design导致时钟区域划分失败
实现 Place / Route / Opt / Timing 社区未闭环 Vivado / Vitis / xilinx:aws-vu9p-f1:shell-v04261818:201920.2
一句话结论:需从opt.dcp在Vivado中实现并完成时序收敛后再在Vitis中复用
生成xclbin时报时钟区域划分失败,需同一时钟布线资源的时钟负载被锁定到重叠时钟区域
ERROR: [Place 30-838] The following clock nets need to use the same clock routing resource, as their clock buffer sources are locked to sites that use the same routing track.
帖中未明确
需从opt.dcp在Vivado中实现并完成时序收敛后再在Vitis中复用
本文据 AMD 客户社区(原 Xilinx 论坛)真实报错帖整理为中文要点,非原文转载;技术细节以原帖与 AMD 官方文档为准。
原帖:https://adaptivesupport.amd.com/s/question/0D52E00006mhE6tSAE/unable-to-disable-physoptdesig…