约束Laguna寄存器位置时出现布局错误
实现 Place / Route / Opt / Timing 社区未闭环 Vivado 2022.1 / Alveo U55C
一句话结论：pblock约束Laguna寄存器位置后出现Place 30-786连接合法性错误
用pblock约束Laguna寄存器位置后，实现阶段出现布局错误
CRITICAL WARNING: [Place 30-786] Connectivity Legality - Laguna TX register [u50_qsfp_i/event_list_0_axis_register_slice/inst/axisc_register_slice_0/gen_multi_slr.multi/triple_slr.slr_slave/gen_slr_common.laguna_s_reset_in_d_reg] does not satisfy following connectivity legality requirements: (1) For UltraScale devices, if there is only one load and the load is a register, then that register can be assigned to RX Laguna site. (2) If there are multiple loads, and some of such loads are flops, then none of the load flops can be assigned to RX site. (3) All loads must be in the other SLR.
帖中未明确；提问者推测该寄存器本应是Laguna RX寄存器而非TX，placer选错了寄存器类型
pblock约束Laguna寄存器位置后出现Place 30-786连接合法性错误
本文据 AMD 客户社区（原 Xilinx 论坛）真实报错帖整理为中文要点，非原文转载；技术细节以原帖与 AMD 官方文档为准。
原帖：https://adaptivesupport.amd.com/s/question/0D54U00007PgirzSAB/i-get-place-errors-when-trying…