ERROR: [Place 30-690]

UltraScale+ PCS/PMA异步LVDS无法布局BITSLICE_CONTROL/RIU_OR

实现 Place / Route / Opt / Timing 已闭环 UltraScale+

现象

同一BYTE_GROUP内实例化多个异步LVDS AXI Ethernet核时布局失败

报错原文

[Place 30-689] Failed to place BITSLICE_CONTROL cell design_1_i/eth_pair_0/mac1/U0/pcs_pma/inst/gen_io_logic/BaseX_Byte_I_Tx_Nibble/Gen_1.Nibble_I_BitsliceCntrl on site BITSLICE_CONTROL_X0Y30 because Instance design_1_i/eth_pair_0/mac1/U0/pcs_pma/inst/gen_io_logic/BaseX_Byte_I_Tx_Nibble/Gen_1.Nibble_I_BitsliceCntrl can not be placed in CONTROL of site BITSLICE_CONTROL_X0Y30 because the bel is occupied by design_1_i/eth_pair_0/mac0/U0/pcs_pma/inst/pcs_pma_block_i/gen_io_logic/BaseX_Byte_I_Tx_Nibble/Gen_1.Nibble_I_BitsliceCntrl. This could be caused by bel constraint conflict. Please check if the cell is used correctly in the design.

根因

帖中未明确；回答建议每个byte group只用一个PCS/PMA核，多lane需在同一核内配置

可尝试的处理步骤

• 每个byte group只使用一个PCS/PMA核
• 同一byte group内多lane时在同一PCS/PMA核中配置lane数
• 每个bank一个PCS/PMA核配置shared logic in core，其余配置shared logic in example design

结论

每个byte group应只用一个PCS/PMA核，多lane在同一核内配置

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