工具链 The-OpenROAD-Project
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
EDA, simulation, synthesis and place-and-route tools — the infrastructure of the FPGA flow.
The project covers topics such as 130nm, asic, caravel, foundry, klayout, magic, netgen, openram.
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