fpga.love ← Back to projects
Home / Projects / hdl_checker

hdl_checker

工具链 suoto

Repurposing existing HDL tools to help writing better code

EDA, simulation, synthesis and place-and-route tools — the infrastructure of the FPGA flow.

The project covers topics such as coc-nvim, emacs-lsp, ghdl, hdl, hdl-checker, language-server, lsp-server, mentor-msim.

This page is auto-synced from the repository metadata and refreshed weekly from GitHub.

Stars228
Forks29
LanguagePython
LicenseGPL-3.0
Last push2026-09-23
Repositoryhttps://github.com/suoto/hdl_checker
View source and README on GitHub

Topics

coc-nvimemacs-lspghdlhdlhdl-checkerlanguage-serverlsp-servermentor-msim

Related projects