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basic_verilog

AI 加速 pConst

Must-have verilog systemverilog modules

Hardware acceleration for neural-network inference and algorithms.

The project covers topics such as altera, debounce, delay, encoder, fifo, fpga, hls, pwm.

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Stars2,032
Forks423
LanguageVerilog
Last push2026-03-12
Repositoryhttps://github.com/pConst/basic_verilog
View source and README on GitHub

Topics

alteradebouncedelayencoderfifofpgahlspwm

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