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chisel

其他 chipsalliance

Chisel: A Modern Hardware Design Language

Open-source work related to the FPGA ecosystem.

The project covers topics such as chip-generator, chisel, chisel3, firrtl, rtl, scala, verilog.

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Stars4,830
Forks666
LanguageScala
LicenseApache-2.0
Last push2026-11-06
Repositoryhttps://github.com/chipsalliance/chisel
Homepagehttps://www.chisel-lang.org/
View source and README on GitHub

Topics

chip-generatorchiselchisel3firrtlrtlscalaverilog

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